Components inside a mobile device generally require high speed interfaces for communication interconnection. Traditionally, the interfaces between the components or modules within a mobile device are CMOS parallel busses operating at low bit rates with slow edges for EMI reasons. These interfaces have become outdated and require a significant extension of the interface bandwidths for the addition of more advanced applications to be incorporated into a mobile device. In order to accomplish this, the MIPI specification was established along with the D-PHY specification, which may be used in combination with the MIPI specification. These specifications may initially be used to provide standard specifications for the connection of a host processor, within a mobile device, to display and camera modules also within the mobile device. The hardware and software design of a mobile device that meets the specifications is up to the manufacturer.
The D-PHY specification may be used by manufacturers to aid with the design of products that adhere to the MIPI alliance specifications for mobile device host processors, display, and camera interfaces. Use of the D-PHY specification may aid in reducing the time-to-market and design costs of mobile devices by standardizing the interfaces between products from different manufacturers. In addition, richer feature sets requiring high bit rates can be realized by implementing the D-PHY standard. Additionally, new features can be added to most mobile devices in a more simplified fashion due to the extensible nature of the MIPI alliance specifications.
A PHY is a functional block that implements the features necessary to communicate over a lane interconnect. A PHY comprises a lane module configured as a clock lane and one or more lane modules configured as data lanes and a PHY adapter layer. A D-PHY is intended to communicate with a bit rate in the order of around 500 Mbits/sec (Mbps), hence the Roman numeral D for 500.
The PHY may use two wires per data lane plus two wires for the clock lane. A lane consists of two complementary lane modules communicating via two-line, point-to-point lane interconnects. Sometimes, a lane is used to denote an interconnect only. Since the PHY may use two wires per data lane plus two wires for the clock lane, there may be foil wires for a minimum PHY configuration. In high-speed mode, each lane is terminated on both sides and driven by a low-swing, differential signal. In low-power mode, all the wires are operated single-ended and non-terminated. For EMI reasons, the drivers for the low power mode are slew-rate controlled and current limited. In certain modes, data is sent over a lane using two wires and having data incorporating a spaced-one-hot approach. A spaced-one-hot approach is a technique for asynchronously sending signal data over a two-wire interface. In a spaced-one-hot approach, two wires are used together to communicate data asynchronously. There are four states defined for the two wires, 0 0 (space), 0 1 (mark-0), 1 0 (mark-1), and 1 1 (stop). The stop state is not for use during normal transmission. All transmissions over the two-wire interface are “Gray” coded so that only one line ever changes at a time. To send a zero bit, the transmitter sends a mark-0 followed by space. To send a one bit, the transmitter sends mark-1 followed by space. So, for example, the pattern 0 1 0 0 1 0 1 1 would look like the sequence shown in FIG. 1.
The lane or the two-wire interface lines (Line 0, Line 1) can pause in any state as shown by the breaks 10 in the timing diagram of FIG. 1. The receiver 14, which receives the data on the line, is expected to recover a clock 12 by generating an exclusive-OR of the two lines (Line 0, Line 1). FIG. 2 depicts a prior art approach to sampling a spaced-one-hot type asynchronous signal that is being received by a prior art digital receiver circuit 14 from two lines 16, 18. The two lines each go to an exclusive-OR component 20 where an exclusive-OR of the two lines is generated at 22. This exclusive-OR result 22 is appropriately delayed by a delay device 24 and then is used to clock the flip-flop 26 and sample the data lines 16, 18 via the flip-flop 26 to determine the identity of the transmitted bit. The rising edge 13 of the clock signal 12 is used as the trigger for the D-flip-flop and output it as the sampled value 28.
The primary disadvantage of the prior art receive circuit, shown in FIG. 2, is that there is a delay element required for delaying the clock signal 22 to the flip-flop 26. This delay element 24 must provide a signal delay that is long enough to ensure that the data will be valid at the D-input 30 of the flip-flop 26 with sufficient set-up time. But, if the delay is too long, the speed of the data link becomes limited by the lengthy delay. Building a reliable delay with these required specifications in digital logic is a tricky endeavor and may require a custom layout element in the silicon/integrated circuit device.
What is needed is an approach for receiving a spaced-one-hot asynchronous signal data over a two-wire interface that does not require a delay element.